Please note, we are experiencing intermittent issues on the platform which we are investigating. You may experience issues with submitting comments. If you do encounter issues, please resubmit your comment. Please accept our apologies for any inconvenience caused

We use cookies to give you the best experience and to help improve our website

Find out what cookies we use and how to disable them

BS IEC 63673 Guidelines for Gate Charge (QG) test method for SIC MOSFET

Source:
IEC
Committee:
EPL/47 - Semiconductors
Categories:
Transistors
Comment period start date:
Comment period end date:
Number of comments:
0

Comment by:

Scope

For SiC MOSFET, the gate-charge characteristic behaves different to conventional silicon power MOSFETs.  The most distinct point is the absence of a real Miller plateau.  Due to short n-channels, which are typically used in SiC MOSFETs, practically a Miller “ramp” is measured.  The standard QG extraction methods [1] cannot be easily applied.  Furthermore, the presence of a VGS,TH hysteresis [2] makes it necessary to define clearly the starting gate voltage for QG measurement and extraction.  The following document defines a QGS,TOT, QGD and QGS,TH which can be extracted from a measured QG waveform. 

The test and extraction method can be applied to the following:           

• N-Channel SiC MOSFET (vertical structure)            

• Wafer and package levels  

Read draft and comment

Comment on proposal

Required form fields are indicated by an asterisk (*) character.


Please email further comments to: debbie.stead@bsigroup.com

Follow standard

You are now following this standard. Weekly digest emails will be sent to update you on the following activities:

You can manage your follow preferences from your Account. Please check your mailbox junk folder if you don't receive the weekly email.

Unfollow standard

You have successfully unsubscribed from weekly updates for this standard.

Error