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Standards Development
This document specifies the principles, test conditions, instruments and equipment, reagents and materials, test procedures, and requirements for test reports of thermal imaging testing methods.
This document is applicable to the defect location of printed boards with interconnect failure after conductive anodic filaments test (CAF), high accelerated temperature and humidity stress test (HAST), interconnect stress test (IST), and thermal shock test (TCT). Other printed circuits and assembly components with interconnect failure can also refer to it.
With the development of PCBs towards high density, high integration, high speed and high frequency, reliability tests such as Conductive Anodic Filament (CAF) test, High Accelerated Temperature and Humidity Stress Test (HAST), Interconnect Stress Test (IST ), and Thermal Cycling Test (TCT) are of great significance for evaluating product quality. Especially, the defect location analysis of interconnects after test failure has become increasingly complex. Currently, IEC has not yet established relevant standa rds for non-destructive defect location analysis of interconnects. At present, most interconnect failure analyses rely on the insulation resistance measurement zoning method for location, but this method requires destructive analysis of the sample, which is very likely to damage the failure point and prevent the acquisition of accurate and complete information. In view of this, there is an urgent need for a new, non -destructive method for interconnect defect location analysis.
The establishment of this standard aims to introduce thermal imaging analysis methods into the circuit board failure analysis process, fill the gap in IEC standards for CAF failure analysis methods, provide the industry with a unified, scientific and non-destructive analysis method, and promote the technological development and standardized application in related fields.
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