British Standards Institution

Source:: IEC
Committee:: EPL/47 - Semiconductors
Categories:: Information management | Standardization. General rules
Comment period start date:: 24/03/2025
Comment period end date:: 06/05/2025

Comment by:

6th May

Scope

This part of IEC 63378-6-2 specifies a type of DXRC standardized by IEC 63378-6. This model is named the Detailed Network thermal Resistance and Capacitance (DNRC) model. The DNRC model is specifically characterized by actual measured values of thermal resistance and heat capacity. The model is designed to predict transient temperatures at the junctions and other specified locations as measured. This document applies to semiconductor packages supported by IEC 63378 -6.

Purpose

The semiconductor package model provided by the semiconductor manufacturer that can evaluate the chip temperature is generally a thermal resistance model in many cases. However, the thermal resistance model is used for steady-state analysis and does not support transient analysis that can estimate the temperature change over time. The standard defines a method for transient thermal analysis of junction temperature with low error by setting up a topology for a transient thermal network model of semiconductor s.

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Please email further comments to: debbie.stead@bsigroup.com

Standard timeline

1. Proposal

Proposal start date:

24/03/2025

Proposal end date:

06/05/2025

2. Draft

3. Public Comments

4. Comment Resolution

5. Approval

6. Publication

Learn more about the standards development process

Standards Development

PNW 47D-989 ED1: Future IEC 63378-6-2 ED1: Thermal standardization on semiconductor packages - Part 6-2: Thermal resistance and capacitance model for transient temperature prediction at junction and measurement points - Model creation met

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