Standards Development

Scope

This document has two purposes; the first is presenting guidelines for the gate dielectric lifetime extraction and wear-out of MOS devices on silicon carbide substrates ("intrinsic behavior").  Specifically, it is designed for MOS devices (capacitors or transistors) where oxide thickness (tox) >> 10 nm. Therefore, ‘soft’ breakdown behavior is not expected to be observed, and oxide breakdown occurs instantaneously as a ‘hard’ breakdown event. Thus, issues relating specifically to thin oxides and soft breakdown are not addressed here. The second purpose is presenting guidelines for the measurement of gate dielectric breakdown, which are assumed to be defect related and occur much earlier than the wear out (“extrinsic behavior”). Although almost all data available in literature is on SiO2 as a gate dielectric, the procedures outlined in this document apply to any dielectric layer. In case of a gate stack of different dielectrics, special care has to be taken when calculating the field distribution across the dielectric stack. This is not covered by this document.

MOS devices such as MOSFETs and IGBTs are designed to be operated at a fixed gate voltage (VGS) level in the ON-state.  As-such, oxide lifetime under controlled gate bias conditions is most appropriate for oxide lifetime extraction. On the other hand, charge to breakdown measurements or constant current stress can provide an alternative way to estimate lifetime, provided some conditions are fulfilled. Practical tests, which give oxide lifetime-related information, are (usually on-wafer and/or packaged devices):

 Constant-voltage stress (CVS) time-dependent dielectric-breakdown (TDDB) testing over short and relatively long time periods.

 Ramped-voltage stress (RVS) or ramped breakdown (RBD) approaches in which data for many samples can be obtained quickly.  A voltage ramp is typically used for this test (V-Ramp), although a current, or current density ramp (J-Ramp), can be performed as well.

 Constant current stress (CCS) time dependent dielectric breakdown testing for low and high current densities.

It should be pointed out that all discussed tests provoke so-called hard-fails. This means that the device is typically “short” after the failure. “Soft” gate oxide failures (only a slight increase of the gate leakage current) as well as fails by parameter shifts were not expected in the typical gate oxide thickness range of SiC-based power-semiconductors. Furthermore, parameters like VTH are typically shifting in such tests, but this is not a topic of interest in the evaluation of the tests.

Testing of gate oxide breakdown under accelerated bias, current or temperature conditions does not replace traditional qualification tests such as high-temperature gate bias (HTGB) testing called for in, for example, JESD22-A108F. This document is not meant to define acceptable lifetime limits, or proscribe acceptable use conditions; that is up to the device manufacturers and users.