Standards Development

Scope

The objective and scope of this document is to establish test methods that replicate latch-up failures during device operation while providing reliable, repeatable latch-up test results from tester to tester, notwithstanding of device type.  This part of IEC 60749-29 establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.  The document will also provide guidelines to allow the user to apply engineering judgement when historical testing methods are not compatible with the integrated circuit’s functionality.

This document applies to a current-injection test (Signal Pin Test) and an overvoltage test (Supply Test).  Current injection is achieved either by current forcing with voltage compliance limit (I Test) or by applying voltage with current compliance limit (E Test).

This document will only consider direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins. Transient induced latch-up will not be addressed. A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.

Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition. Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.

All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, optoelectronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are evaluated according to this document.  This test method is applicable to NMOS, CMOS, bipolar, and all variations and combinations of these technologies including some Silicon-On-Insulator (SOI).

Transient induced latch-up is not considered; therefore, this document only considers direct current injection into and out of a signal pin (formerly called I/O pin), and overvoltage on the power supply pins.  A transient-induced latch-up characterization methodology is defined in the ANSI/ESD Standard Practice SP5.4.1-2017 “Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits – Transient Latch-up Testing, Device Level”.

Latch-up failures are limited to the detection of a sustained low-impedance path resulting from an applied trigger condition.  Other types of potential functional failures, including logic state changes and spurious resets, are not considered by this document, and are not considered latch-up failures.