Standards Development

Scope

This document defines functional descriptions and requirements for the Hardware Abstraction Layer (HAL) within the quantum computing software stack, while specific implementation values remain out of scope. The HAL sits between the assembly layer and the control software layer (with an ISA), as described in TR 18202:2025 (“Layer Models for Quantum Computing.”). Its purpose is to provide a standardized interface that abstracts away hardware-specific details and exposes essential capabilities to higher layers, enabling portability and interoperability across diverse quantum architectures.

The HAL is designed to support a wide range of quantum hardware platforms, each with unique characteristics such as qubit topology, native gate sets, and error correction schemes. Rather than prescribing strict implementation details, this TS focuses on defining the functionalities of the HAL, including instruction translation, resource management, virtualization for multi-user environments, and reporting of hardware capabilities. These functionalities allow compilers and programming frameworks to optimize execution without requiring direct interaction with proprietary hardware interfaces.

This “Part 1” of the TS is structured to accommodate future developments and revisions, leaving detailed specifications of interfaces and parameter values for subsequent parts. It is not necessary to describe all possible hardware architectures before publishing this part; however, it must provide sufficient detail to enable higher layers to be standardized in complementary documents. By establishing these foundational requirements, the HAL becomes a cornerstone for modular quantum computing systems, ensuring flexibility, scalability, and vendor-neutral integration.

Purpose

The proposal is to create a first TS about the “Hardware Abstraction Layer” (HAL), which concentrates on a dedicated layer within TR 18202:2025 (“Layer Model of Quantum Computing”). It aims at creating functional descriptions and functional requirements of relevant functionalities within the HAL

The importance of a Hardware Abstraction Layer in modular quantum computing is rapidly increasing as the ecosystem expands to include hardware and software products from multiple vendors. This growth creates a strong need for a TS that ensures interoperability and portability across diverse quantum platforms. The HAL enables higher-level software and compilers to operate independently of hardware-specific details, allowing customers, such as research institutes and system integrators, to combine components from different vendors into a single, cohesive quantum system. This approach mirrors the success of abstraction layers in classical computing, which fueled the rise of modular architectures and accelerated market adoption. For quantum computing, such modularity can only succeed if the HAL provides well-defined, standardized interfaces that support instruction translation, resource management, and hardware capability reporting. These interfaces must offer access to well-described functionalities within the HAL to guarantee compatibility, scalability, and security across the supply chain. By formalizing these aspects, the HAL becomes a cornerstone for building flexible, vendor-neutral quantum computing stacks.

It is expected that a full specification of the HAL will be developed in parts, where the first part concentrates on functional descriptions and functional requirements only. The word “functional” means within this context that a precise definition of interfaces, information flows (via instructions, commands, signals, etc) and values is out of scope of this first part, and that this first part mainly concentrates on general descriptions of what layers should support and which properties or quantities are to be considered for future specification.

Currently the latest results are in TR 18202:2025, which describes the layer model as a whole. It gives the outline of the hardware abstraction layer in relation to the other layers.